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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd16717 384-output tft-lcd source driver (compatible with 64-gray scales) data sheet document no. s15375ej1v0ds00 (1st edition) date published january 2002 ns cp (k) printed in japan description the pd16717 is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.2 v to v dd2 ? 0.2 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequency of 55 mhz when driving at 2.5 v, this driver is applicable to xga-standard tft-lcd panels and sxga tft-lcd panels. features ? cmos level input (2.5 to 3.6 v) ? 384 outputs ? input of 6 bits (gray-scale data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter (r-dac) ? logic power supply voltage (v dd1 ): 2.5 to 3.6 v ? driver power supply voltage (v dd2 ): 8.5 v 0.5 v ? high-speed data transfer: f clk = 55 mhz (internal data transfer speed when operating at v dd1 = 2.5 v) ? output dynamic range: v ss2 + 0.2 v to v dd2 ? 0.2 v ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? input data inversion function (pol2) ? through rate control inversion function (src) ? output reset control inversion function (mode) ? slim chip ordering information part number package pd16717n-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, so please contact one of our sales representatives. the mark shows major revised points.
data sheet s15375ej1v0ds 2 pd16717 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 to v 9 pol d 00 to d 05 c 1 c 2 c 63 c 64 stb clk 64-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 to d 15 d 20 to d 25 s 3 s 384 pol2 d 30 to d 35 d 40 to d 45 d 50 to d 55 src mode remark /xxx indicates active low si gnal. 2. relationship between output circuit and d/a converter s 1 s 2 s 383 6-bit d/a converter s 384 v 4 5 5 pol multi- plexer v 9 v 0 v 5
data sheet s15375ej1v0ds 3 pd16717 3. pin configuration ( pd16717) (copper foil surface, face-up) s 384 s 383 sthl d 55 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 r , /l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 mode v 4 v 3 v 2 v 1 v 0 v ss1 src clk stb pol pol2 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 d 02 d 01 s 3 d 00 s 2 sthr s 1 co pp er foil surface remark this figure does not specify the tcp package.
data sheet s15375ej1v0ds 4 pd16717 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 384 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input these refer to the shift direction control input pins when driver ics are connected in cascade. the shift directions of the shift registers are as follows. r,/l = h (right shift): sthr (input), s 1 s 384 , sthl (output) r,/l = l (left shift) : sthl (input), s 384 s 1 , sthr (output) sthr right shift start pulse i/o sthl left shift start pulse i/o these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = h (right shift): sthr input, sthl output r,/l = l (left shift): sthl input, sthr output a high level should be input as the pulse of one cycle of the clock signal. if the start pulse input is more than 2clk, the first 1clk of the high-level input is valid. clk shift clock input refers to the shift register?s shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. if 66th clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stb?s rising edge. this pin should not stop during blanking period. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. output timing of gray scale voltage is changed by setting mode. mode = h or open: stb at the falling edge, the gray scale voltage is supplied to the driver. mode = l: after set to stb = h, the gray scale voltage is supplied by the rising edge behind 3 clo cks. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n?1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol2 data inversion input data inversion can invert when display data is loaded. pol2 = h: data inversion inverts display data inside ic. pol2 = l: data inversion does not invert input data. when in stb = h, it becomes test mode if pol2 is changed, throughout stb = h period should not carry out the change of pol2.
data sheet s15375ej1v0ds 5 pd16717 (2/2) pin symbol pin name i/o description mode output reset control input mode = h or open: output reset. stb at the falling edge, the gray scale voltage is supplied to the driver. mode = l: non-output reset. after set to stb = h, the gray scale voltage is supplied by the rising edge behind 3 clo cks. this pin is pulled up to the v dd2 power supply inside the ic. src high driving time control input this pin is set up to high drive time by the multiple of stb width. src = h or open: high drive time is twice the stb width. src = l: high drive time is three times the stb width. refer to 9. src pin and high driving time this pin is pulled up to the v dd1 power supply inside the ic. v 0 to v 9 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.2 v v dd1 logic power supply ? 2.5 to 3.6 v v dd2 driver power supply ? 8.5 v 0.5 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down (simultaneous power application to v dd2 and v 0 to v 9 is possible.). 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also recommended between the -corrected power supply terminals (v 0 , v 1 , v 2 ,....., v 9 ) and v ss .
data sheet s15375ej1v0ds 6 pd16717 5. relationship between input data and output voltage value the pd16717 incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to the common voltage figure 5?1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships of v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.2 v figures 5?2 and 5?3 indicate the relationship between the input data and output voltage and the resistance values of the resistor string. figure 5?1. relationship between input data and -corrected power supplies 0.1 v 0.1 v v dd2 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 0.5 v dd2 v 9 v ss2 00 10 20 30 3f input data (hex) 15 15 16 16 16 16 16 16 split interval
data sheet s15375ej1v0ds 7 pd16717 figure 5?2. -corrected voltages and ladder resistors ratio v 0 ' v 17 ' v 1 ' v 47 ' v 2 ' v 48 ' v 3 ' v 49 ' v 15 ' v 16 ' v 63 ' v 61 ' v 62 ' r 0 r 17 r 1 r 47 r 46 r 2 r 48 r 3 r49 r 14 r 15 r 16 r 60 r 61 r 62 v 4 v 3 v 1 v 0 v 17 '' v 0 '' v 16 '' v 15 '' v 2 '' v 1 '' v 63 '' v 62 '' v 61 '' v 49 '' v 48 '' v 47 '' r 61 r 60 r 59 r 49 r 48 r 47 r 46 v 6 r 62 v 5 r 17 r 0 r 16 r 15 r 14 r 2 r 1 v 9 v 8 v 60 '' caution there is no connection between v 4 and v 5 terminal in the chip. rn ratio r0 6.2 r1 5.8 r2 5.4 r3 5.1 r4 4.7 r5 4.3 r6 4.3 r7 3.9 r8 3.9 r9 3.1 r10 3.1 r11 2.7 r12 2.7 r13 2.7 r14 2.3 r15 2.3 r16 2.0 r17 1.8 r18 1.8 r19 1.7 r20 1.6 r21 1.5 r22 1.5 r23 1.4 r24 1.3 r25 1.3 r26 1.2 r27 1.2 r28 1.1 r29 1.1 r30 1.0 r31 1.0 r32 1.0 r33 1.0 r34 1.0 r35 1.0 r36 1.0 r37 1.0 r38 1.0 r39 1.0 r40 1.0 r41 1.0 r42 1.0 r43 1.0 r44 1.0 r45 1.0 r46 1.0 r47 1.0 r48 1.1 r49 1.1 r50 1.1 r51 1.1 r52 1.1 r53 1.6 r54 1.6 r55 1.6 r56 1.6 r57 1.6 r58 2.1 r59 2.7 r60 3.4 r61 5.2 r62 11.2
data sheet s15375ej1v0ds 8 pd16717 figure 5?3. relationship between input data and output voltage (pol2 = l) (output voltage 1) v dd2 ? 0.2 v v 5 > v 6 > v 7 > v 8 > v 9 0.5 v dd2 (output voltage 2) 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.2 v input data 00h v 0' v 0 v 0'' v 9 01h v 1' v 1 +(v 0 -v 1 ) 56.4 / 62.6 v 1'' v 9 +(v 8 -v 9 ) 6.2 / 62.6 02h v 2' v 1 +(v 0 -v 1 ) 50.6 / 62.6 v 2'' v 9 +(v 8 -v 9 ) 12.1 / 62.6 03h v 3' v 1 +(v 0 -v 1 ) 45.1 / 62.6 v 3'' v 9 +(v 8 -v 9 ) 17.5 / 62.6 04h v 4' v 1 +(v 0 -v 1 ) 40.1 / 62.6 v 4'' v 9 +(v 8 -v 9 ) 22.6 / 62.6 05h v 5' v 1 +(v 0 -v 1 ) 35.4 / 62.6 v 5'' v 9 +(v 8 -v 9 ) 27.2 / 62.6 06h v 6' v 1 +(v 0 -v 1 ) 31.1 / 62.6 v 6'' v 9 +(v 8 -v 9 ) 31.5 / 62.6 07h v 7' v 1 +(v 0 -v 1 ) 26.8 / 62.6 v 7'' v 9 +(v 8 -v 9 ) 35.8 / 62.6 08h v 8' v 1 +(v 0 -v 1 ) 22.9 / 62.6 v 8'' v 9 +(v 8 -v 9 ) 39.7 / 62.6 09h v 9' v 1 +(v 0 -v 1 ) 19.1 / 62.6 v 9'' v 9 +(v 8 -v 9 ) 43.6 / 62.6 0ah v 10' v 1 +(v 0 -v 1 ) 15.9 / 62.6 v 10'' v 9 +(v 8 -v 9 ) 46.7 / 62.6 0bh v 11' v 1 +(v 0 -v 1 ) 12.8 / 62.6 v 11'' v 9 +(v 8 -v 9 ) 49.8 / 62.6 0ch v 12' v 1 +(v 0 -v 1 ) 10.1 / 62.6 v 12'' v 9 +(v 8 -v 9 ) 52.5 / 62.6 0dh v 13' v 1 +(v 0 -v 1 ) 7.4 / 62.6 v 13'' v 9 +(v 8 -v 9 ) 55.2 / 62.6 0eh v 14' v 1 +(v 0 -v 1 ) 4.7 / 62.6 v 14'' v 9 +(v 8 -v 9 ) 57.9 / 62.6 0fh v 15' v 1 +(v 0 -v 1 ) 2.3 / 62.6 v 15'' v 9 +(v 8 -v 9 ) 60.3 / 62.6 10h v 16' v 1 v 16'' v 8 11h v 17' v 2 +(v 1 -v 2 ) 20.7 / 22.6 v 17'' v 8 +(v 7 -v 8 ) 2.0 / 22.6 12h v 18' v 2 +(v 1 -v 2 ) 18.8 / 22.6 v 18'' v 8 +(v 7 -v 8 ) 3.8 / 22.6 13h v 19' v 2 +(v 1 -v 2 ) 17.0 / 22.6 v 19'' v 8 +(v 7 -v 8 ) 5.7 / 22.6 14h v 20' v 2 +(v 1 -v 2 ) 15.3 / 22.6 v 20'' v 8 +(v 7 -v 8 ) 7.4 / 22.6 15h v 21' v 2 +(v 1 -v 2 ) 13.7 / 22.6 v 21'' v 8 +(v 7 -v 8 ) 9.0 / 22.6 16h v 22' v 2 +(v 1 -v 2 ) 12.1 / 22.6 v 22'' v 8 +(v 7 -v 8 ) 10.5 / 22.6 17h v 23' v 2 +(v 1 -v 2 ) 10.7 / 22.6 v 23'' v 8 +(v 7 -v 8 ) 12.0 / 22.6 18h v 24' v 2 +(v 1 -v 2 ) 9.3 / 22.6 v 24'' v 8 +(v 7 -v 8 ) 13.4 / 22.6 19h v 25' v 2 +(v 1 -v 2 ) 7.9 / 22.6 v 25'' v 8 +(v 7 -v 8 ) 14.7 / 22.6 1ah v 26' v 2 +(v 1 -v 2 ) 6.7 / 22.6 v 26'' v 8 +(v 7 -v 8 ) 16.0 / 22.6 1bh v 27' v 2 +(v 1 -v 2 ) 5.4 / 22.6 v 27'' v 8 +(v 7 -v 8 ) 17.2 / 22.6 1ch v 28' v 2 +(v 1 -v 2 ) 4.2 / 22.6 v 28'' v 8 +(v 7 -v 8 ) 18.4 / 22.6 1dh v 29' v 2 +(v 1 -v 2 ) 3.1 / 22.6 v 29'' v 8 +(v 7 -v 8 ) 19.5 / 22.6 1eh v 30' v 2 +(v 1 -v 2 ) 2.0 / 22.6 v 30'' v 8 +(v 7 -v 8 ) 20.6 / 22.6 1fh v 31' v 2 +(v 1 -v 2 ) 1.0 / 22.6 v 31'' v 8 +(v 7 -v 8 ) 21.6 / 22.6 20h v 32' v 2 v 32'' v 7 21h v 33' v 3 +(v 2 -v 3 ) 15.0 / 16.0 v 33'' v 7 +(v 6 -v 7 ) 1.0 / 16.0 22h v 34' v 3 +(v 2 -v 3 ) 14.0 / 16.0 v 34'' v 7 +(v 6 -v 7 ) 2.0 / 16.0 23h v 35' v 3 +(v 2 -v 3 ) 13.0 / 16.0 v 35'' v 7 +(v 6 -v 7 ) 3.0 / 16.0 24h v 36' v 3 +(v 2 -v 3 ) 12.0 / 16.0 v 36'' v 7 +(v 6 -v 7 ) 4.0 / 16.0 25h v 37' v 3 +(v 2 -v 3 ) 11.0 / 16.0 v 37'' v 7 +(v 6 -v 7 ) 5.0 / 16.0 26h v 38' v 3 +(v 2 -v 3 ) 10.0 / 16.0 v 38'' v 7 +(v 6 -v 7 ) 6.0 / 16.0 27h v 39' v 3 +(v 2 -v 3 ) 9.0 / 16.0 v 39'' v 7 +(v 6 -v 7 ) 7.0 / 16.0 28h v 40' v 3 +(v 2 -v 3 ) 8.0 / 16.0 v 40'' v 7 +(v 6 -v 7 ) 8.0 / 16.0 29h v 41' v 3 +(v 2 -v 3 ) 7.0 / 16.0 v 41'' v 7 +(v 6 -v 7 ) 9.0 / 16.0 2ah v 42' v 3 +(v 2 -v 3 ) 6.0 / 16.0 v 42'' v 7 +(v 6 -v 7 ) 10.0 / 16.0 2bh v 43' v 3 +(v 2 -v 3 ) 5.0 / 16.0 v 43'' v 7 +(v 6 -v 7 ) 11.0 / 16.0 2ch v 44' v 3 +(v 2 -v 3 ) 4.0 / 16.0 v 44'' v 7 +(v 6 -v 7 ) 12.0 / 16.0 2dh v 45' v 3 +(v 2 -v 3 ) 3.0 / 16.0 v 45'' v 7 +(v 6 -v 7 ) 13.0 / 16.0 2eh v 46' v 3 +(v 2 -v 3 ) 2.0 / 16.0 v 46'' v 7 +(v 6 -v 7 ) 14.0 / 16.0 2fh v 47' v 3 +(v 2 -v 3 ) 1.0 / 16.0 v 47'' v 7 +(v 6 -v 7 ) 15.0 / 16.0 30h v 48' v 3 v 48'' v 6 31h v 49' v 4 +(v 3 -v 4 ) 36.7 / 37.8 v 49'' v 6 +(v 5 -v 6 ) 1.1 / 37.8 32h v 50' v 4 +(v 3 -v 4 ) 35.7 / 37.8 v 50'' v 6 +(v 5 -v 6 ) 2.1 / 37.8 33h v 51' v 4 +(v 3 -v 4 ) 34.6 / 37.8 v 51'' v 6 +(v 5 -v 6 ) 3.2 / 37.8 34h v 52' v 4 +(v 3 -v 4 ) 33.5 / 37.8 v 52'' v 6 +(v 5 -v 6 ) 4.2 / 37.8 35h v 53' v 4 +(v 3 -v 4 ) 32.5 / 37.8 v 53'' v 6 +(v 5 -v 6 ) 5.3 / 37.8 36h v 54' v 4 +(v 3 -v 4 ) 30.9 / 37.8 v 54'' v 6 +(v 5 -v 6 ) 6.9 / 37.8 37h v 55' v 4 +(v 3 -v 4 ) 29.3 / 37.8 v 55'' v 6 +(v 5 -v 6 ) 8.5 / 37.8 38h v 56' v 4 +(v 3 -v 4 ) 27.7 / 37.8 v 56'' v 6 +(v 5 -v 6 ) 10.1 / 37.8 39h v 57' v 4 +(v 3 -v 4 ) 26.1 / 37.8 v 57'' v 6 +(v 5 -v 6 ) 11.7 / 37.8 3ah v 58' v 4 +(v 3 -v 4 ) 24.5 / 37.8 v 58'' v 6 +(v 5 -v 6 ) 13.3 / 37.8 3bh v 59' v 4 +(v 3 -v 4 ) 22.4 / 37.8 v 59'' v 6 +(v 5 -v 6 ) 15.4 / 37.8 3ch v 60' v 4 +(v 3 -v 4 ) 19.7 / 37.8 v 60'' v 6 +(v 5 -v 6 ) 18.1 / 37.8 3dh v 61' v 4 +(v 3 -v 4 ) 16.4 / 37.8 v 61'' v 6 +(v 5 -v 6 ) 21.4 / 37.8 3eh v 62' v 4 +(v 3 -v 4 ) 11.2 / 37.8 v 62'' v 6 +(v 5 -v 6 ) 26.6 / 37.8 3fh v 63' v 63'' out p ut volta g e1 out p ut volta g e2 v 4 v 5 caution there is no connection between v 4 and v 5 terminal in the chip.
data sheet s15375ej1v0ds 9 pd16717 6. relationship between input data and output pin data format : 6 bits x 2 rgbs (6 dots) input width : 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 ... s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s3 s4 ... s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n?1 (odd output), s 2n (even output)
data sheet s15375ej1v0ds 10 pd16717 7. relationship between stb, clk, and output waveform (mode =l) this chapter indicates relationship between stb, clk, and output waveform in the pd16717. in figure 7 ? 2, stb = h is taken in by the rising edge of clk [1]. however, when not satisfying the standard of t stb - clk , stb = h is taken in by the rising edge of the next clk [1?]. the latch of display data is completed by the falling edge of the next clk which took in stb = h. moreover, synchronizing with the rising edge of the next clk, driver output is started after the completion of a display data latch. therefore, in order to output the gray scale voltage, it is at least 3 clock necessity. figure 7?1. output circuit block diagram dac + sw1 s n (vx) output amp figure 7?2. output circuit block diagram [ 1 ] [ 1' ] t stb-clk clk stb sn (vx) sw1:off hi-z
data sheet s15375ej1v0ds 11 pd16717 8. relationship between mode, stb, pol and output waveform mode = h or open: a total output serves as reset (short circuit), and throughout stb = h outputs gray scale voltage to the lcd panel synchronizing with the falling edge of stb. mode = l: this is set to stb = h and a 2 clock cycle all output outputs gray scale voltage to the lcd panel after hi-z. refer to 7. relationship between stb, clk, and output waveform (mode = l). figure 8?1. mode = h or open reset stb pol s 2n s 2n ? 1 reset reset internal bias current output amplifier high driviving time (two or three times by stb width) selected voltage of v 0 to v 4 selected voltage of v 0 to v 4 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9 figure 8?2. mode = l stb pol s 2n s 2n ? 1 hi-z hi-z hi-z internal bias current output amplifier high driviving time (two or three times by stb width) selected voltage of v 0 to v 4 selected voltage of v 0 to v 4 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9
data sheet s15375ej1v0ds 12 pd16717 9. src pin and high driving time the pd16717 has a current consumption of selection or driver ic simple substance is the high drive time of output amplifier controllable by the logic of src pin. src = h or open: high drive time is twice the stb width. src = l: high drive time is three times the stb width. high drive time at counting the clock has decided in stb period, and the relationship is as follows. the high drive time of table is the number of clocks from stb falling. table 9?1. relationship between number of clocks in stb period and high drive time high driving time clk in stb period src = h or open (unit: clk) src = l (unit: clk) under 7clk 8 16 8 to 15clk 16 32 16 to 23clk 24 48 24 to 31clk 32 64 32 to 39clk 40 80 40 to 47clk 48 96 48 to 55clk 56 112 56 to 63clk 64 128 64 to 71clk 72 144 72 to 79clk 80 160 80 to 87clk 88 176 88 to 95clk 96 192 96 to 103clk 104 208 104 to 111clk 112 224 112clk or up prohibited in consideration of the characteristic of the lcd panel, after the system estimates sufficient, please decide on the high driving time of output amplifier.
data sheet s15375ej1v0ds 13 pd16717 10. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +10.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic part supply voltage v dd1 2.5 3.6 v driver part supply voltage v dd2 8.0 8.5 9.0 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.3 v dd1 v v 0 to v 4 0.5 v dd2 v dd2 ? 0.2 v -corrected voltage v 5 to v 9 0.2 0.5 v dd2 v driver part output voltage v o v ss2 + 0.2 v dd2 ? 0.2 v clock frequency f clk 55 mhz
data sheet s15375ej1v0ds 14 pd16717 electrical characteristics (t a = ?10 to +75 c, v dd1 = 2.5 to 3.6 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit exclude mode, src 1.0 a input leak current i il mode, src t.b.d. a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance r v 0 to v 4 = v 5 to v 9 = 4.0 v 9.8 13.8 23.0 k ? i voh v x = 7.0 v, v out = 6.5 v note ?300 a driver output current i vol v x = 1.0 v, v out = 1.5 v note 300 a output voltage deviation ? v o 7 20 mv output swing difference deviation ? v p?p v dd1 = 3.3 v, v dd2 = 8.5 v, v out = 2.0 v, 4.25 v, 6.5 v, t a = 25c 2 30 mv logic part dynamic current consumption i dd1 v dd1 3.2 6.0 ma driver part dynamic current consumption i dd2 v dd2 , with no load 4.6 7.0 ma note v x refers to the output voltage of analog output pins s 1 to s 384 . v out refers to the voltage applied to analog output pins s 1 to s 384 . cautions 1. f stb = 65 khz, f clk = 54 mhz 2. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades are connected under the assumption of xga single-sided mounting (10 units). switching characteristics (t a = ?10 to +75 c, v dd1 = 2.5 to 3.6 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit c l = 15 pf, v dd1 = 2.5 to 3.6 v 10 17 ns start pulse delay time t plh1 c l = 15 pf, v dd1 = 3.0 to 3.6 v 8 10.5 ns t plh2 (2.5) s t plh3 (4) s t phl2 (2.5) s driver output delay time t phl3 c l = 75 pf, r l = 5 k ? (4) s c i1 exclude sthr (sthl), t a = 25c 10 pf input capacitance c i2 sthr (sthl),t a = 25c 15 pf output r l2 r l3 r l4 r l5 r ln = 1 k ? c l1 c l2 c l3 c l4 c l5 c ln = 15 pf r l1 measure point
data sheet s15375ej1v0ds 15 pd16717 timing requirements (t a = ?10 to +75 c, v dd1 = 2.5 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 18 ns clock pulse high period pw clk(h) 4ns 2.5 v v dd1 < 3.0 v 6 ns clock pulse low period pw clk(l) 3.0 v v dd1 3.6 v 4 ns data setup time t setup1 2ns data hold time t hold1 2ns start pulse setup time t setup2 2ns start pulse hold time t hold2 2ns pol21/22 setup time t setup3 2ns pol21/22 hold time t hold3 2ns stb pulse width pw stb 3 111 clk last data timing t ldt 2clk clk-stb time t clk-stb clk stb 6ns stb-clk time t stb-clk stb clk 9ns time between stb and start pulse t stb-sth stb sthr(sthl) 2clk pol-stb time t pol-stb pol or stb ?5 ns stb-pol time t stb-pol stb pol or 6ns remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
data sheet s15375ej1v0ds 16 pd16717 switching characteristic waveform (r,/l= h, mode = h or open) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol sn (v x ) stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3646566 701 702 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 target voltage +0.1 v dd2 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 373 to d 378 d 379 to d 384 d 385 to d 390 d 4195 to d 4200 invalid invalid v dd1 v ss1 t setup3 t hold3 pol2 (1st dr.) (1st dr.) invalid t phl3 t phl2 t plh2
data sheet s15375ej1v0ds 17 pd16717 switching characteristic waveform(r,/l= h, mode =l) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol sn (v x ) stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3646566 701 702 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage +0.1 v dd2 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 373 to d 378 d 379 to d 384 d 385 to d 390 d 4195 to d 4200 invalid invalid v dd1 v ss1 t setup3 t hold3 pol2 (1st dr.) (1st dr.) invalid
data sheet s15375ej1v0ds 18 pd16717 11. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16717. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16717n- xxx : tcp (tab pack age) mounting condition mounting method condition soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100 c : pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s15375ej1v0ds 19 pd16717 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16717 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of january, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual pr operty rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of cust omer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if cust omers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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